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ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
latches low and the internal GATE pulldown circuitry is
activated and pulls GATE low only when both of the
conditions are satisfied:
1) V OVI ≥ 0.6V.
2) V IN ≥ V BUS .
OVP can sink 10mA maximum. Cycle power or pull
UVLO low and then high again to reset the OVP latch.
GATE is pulled to PGND and remains low as long as
V OVI ≥ 0.6V. When V OVI drops below 0.6V, OVP remains
low. However, the MAX5079 tries to turn on the ORing
MOSFET unless V IN is actively kept below the undervolt-
age lockout. Use OVP to drive the cathode of an opto-
coupler to shut down the respective power supply from
the primary side (see the Typical Application Circuit of
Figure 2) or fire an SCR connected from IN to PGND.
Power-Good Comparator (PGOOD)
PGOOD output pulls low when V UVLO falls below 0.6V
or V OVI goes above 0.6V. PGOOD can sink a maximum
of 2mA.
Layout Guidelines
1) Place a 1μF ceramic input bypass capacitor physi-
cally close to IN and PGND. Connect IN as close as
possible to the source of the ORing MOSFET.
2) Sense the V BUS close to the bulk capacitor, away from
the drain of the ORing MOSFET. When IN is shorted to
ground during a fault, BUS is also pulled low through
the ORing MOSFET. In the absence of V AUXIN , the
MAX5079 loses both power inputs V IN and V BUS . This
can cause a delayed pulldown of the gate. Sensing
the BUS away from the ORing MOSFET drain, close to
the BUS bulk capacitor provides power to the
MAX5079 for a few microseconds, long enough to pull
down the ORing MOSFET gate and isolate BUS from a
shorted IN.
3) Place the charge-pump capacitor (C EXT ) and the
slow-comparator blanking time adjustment capacitor
(C STH ) as close as possible to the MAX5079.
4) Run a thick trace from the gate of the ORing MOSFET
to GATE.
14
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